1. Field of the Invention
The present invention relates to a layer number estimation device and the like, for a BGA component mounting substrate on which a BGA component is mounted, for estimating the number of wiring layers required for drawing wirings out of electrodes connected with pins of a BGA (ball grid array) component to the periphery. Note that a BGA component means a wiring board or a semiconductor chip having a BGA structure, in which a large number of pins are provided on an area from the peripheral side to the center side. A BGA component mounting substrate means a printed board or an LSI package, on which a BGA component is mounted. Further, electrodes on the BGA component side are called pins herein.
2. Related Art
Conventional art for estimating the number of vias and layers is described in, for example, Japanese Patent Application Laid-open No. 2000-331038, as a rough wiring route layer assignment system. FIG. 1 is a block diagram showing this conventional art. Hereinafter, explanation will be given based on this Figure.
A layer assigning device 102 is composed of an area extraction means 121, a route intersection extraction means 122, a non-intersecting route set extraction means 123, a layer assigning means 124, and an assignment adjusting means 125. The route intersection extraction means 122 extracts intersection information showing intersections of rough wiring routes existing in an area selected by the area extraction means 125. The non-intersection route set extraction means 123 classifies and extracts non-intersection route sets of the number less than the number of wiring layers from the rough wiring route sets within the area by referring to the intersection information, and extracts rough wiring routes, not belonging to either non-intersection route set, as elements of remaining route sets. The layer assigning means 124 performs layer assignment for detailed wirings relating to the area by referring to the intersection information, the non-intersection route sets and the remaining route sets. The assignment adjusting means 125 judges whether the layer assignment performed by the layer assigning means 124 is executable, and if judges that it is “non-executable”, adjusts the layer assignment. This enables to estimate the number of vias accurately, and to minimize the number of vias required for detailed wiring, in multilayer wiring designs for an integrated circuit and a printed board.
However, the conventional art has a problem of taking time for processing, since estimation of the number of layers is carried out while searching for wiring routes.